Ontwikkeling van PML simulasie-sagteware

Abstract

Programmable logic offers a favourable vari~ty of logic applications and is importance in digital designs. solution to a of increasing The work in this project concerns the development of a complete set of software for the implementation of a var iety of Programmable array logic (PAL) dev ices. The software consists of the following programs: • PAL database software: A large amount of information regarding the specif ic component is needed for the determination of the fuse map, preparation of the JEDEC file and simulation of the expected operation of a PAL. The necessary information is made available to the system by the execution of this program. • Fuse map software : The user of a PAL specifies the desired operation thereof by means of Boolean expressions. The program which has been developed makes the input and modification of such expressions possible. It also produce a schematic representation of the programmed PAL for evaluation by the user . Commercial PAL programmers use JEDEC files as input . Such files can also be compiled and stored with this software. • Simulation software : The user of a PAL can verify the correctness of a Boolean expression by simulating the expected operation of a PAL which has been programmed in this way. This simulation is performed by using the relevant JEDEC file. During simulation, input stimuli for the circuit are selected randomly by the operator, and the expected operation of the PAL is represented in the form of a truth table. Evaluation of the software : Correct operation of the software was verified by the practical implementation of a variety of designs . A number of these circuits were used in unrelated projects and satisfactory results have been achieved. Particular knowledge regarding the following has been obtained: • Characteristics and programming of PALs . • Format and construction of JEDEC files. • Principles and applications of simulation of electronic circuits in general and PALs in particular.